The present invention relates generally to integrated circuits, and more particularly, to a synchronous clock generator used in such circuits.
Integrated circuits receive an input signal from an external device. The integrated circuit executes processing operations, and then generates an output signal. Clock signals are used to control the flow of the input signal into, through, and out of the integrated circuit. Operations on the input signal are often initiated at the edges of a clock signal.
Executing operations on an edge of a clock signal may be complex. Data may arrive substantially at the same time with the rising edge of the clock signal and may be immediately latched into data registers. The data, however, may require sufficient time to transition between high and low levels. Thus the data may not be latched during a large portion of a clock period during the transition period.